DisplayPort 2.1 – Trilinear’s Complete Solution
Trilinear Technologies’ latest delivers today’s most innovative display solution while accelerating your time to market.
PHY Integration: No Shortcuts, Stronger Results
PHY Integration is an essential process for any design and technology project. Setting it up right the first time is both the fastest and most efficient way you can be confident in your product long-term. We’ll tell you how we do it, how we ensure that it works, and how we’re the best people to get it done.
Trilinear Technologies Gen6 Release
New DisplayPort Controllers Include DisplayPort 2.0, Embedded DisplayPort 1.5, and Integrated DSC 1.2a Support
Display Stream Compression (DSC) Encode and Decode Solutions added to our IP Portfolio.
Meet the newest members of its M-series video compression IP core family, the M25 DSC 1.2 Decoder and M27 DSC 1.2 Encoder. With its high performance, low cost implementation, the Display Stream Compression encoder and decoder cores can be integrated into System-on-Chips (SoCs) or FPGAs for a wide range of applications including consumer electronics, professional video editing, broadcast, medical and surveillance applications.
Advancing Industry-Leading DisplayPort Transmitter and Receiver Link Controllers.
Continuing the highly successful line of DisplayPort link controller cores, the Trilinear VF-111T DisplayPort Transmitter and VF-117R DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.4 standard. The fifth generation cores are available for implementation in FPGA or ASIC devices utilizing a variety of physical layer (PHY) interfaces available through third party partners. Both the Transmitter and Receiver are currently implemented for evaluation in multiple FPGA platforms.
Delivering Next-Generation DisplayPort Controllers for Multiple FPGA and ASIC Tech
Our latest DisplayPort Transmitter and DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.3a standard and the Embedded DisplayPort 1.4 standard. With the latest round of improvements, Trilinear has added compliance with the latest VESA standards and support for multiple silicon PHY implementations available in process nodes from 55nm to 14nm. Both cores are currently implemented for evaluation in Xilinx FPGAs.
