We craft leading-edge, highly integrated IP cores that run DisplayPort interfaces for top global organizations across every industry.
Our VESA-compliant, proprietary cores give you the power to design product faster, shorten time-to-market, and reduce overall costs—all with cores that never fail, regardless of design requirements.
DisplayPort IP
The only complete solution
Transmitters & Receivers
Next-gen DisplayPort 1.4 transmitter and receiver Link Controllers that target multiple FPGA and ASIC technologies—providing a unique internal architecture that allows integration into both FPGA and ASIC target environments, with no loss of performance.
Encoders & Decoders
Real-time DSC 1.2 encode and decode solutions that support realtime operations with high performance and low cost implementation. DSC encoder and decoder cores integrate into SoCs or FPGAs for a wide range of applications across industries, from broadcast to surveillance.
Plus, all the software
Our DisplayPort cores come fully packaged with all the software you need to keep chaos at bay. Each stack is tested for compliance and compatibility with existing production devices—fully validated with multiple compilers, including x86, RISC-V, and ARM.
Here’s the truth.
By the time your project gets to us, you’re already weeks if not months behind schedule. Constraints are tighter. Your budget is smaller. And your margin for error has all but evaporated. Those are just the facts.
We get it. And we got you.
Our custom, VESA-compliant, and fully complete DisplayPort solutions provide your teams with the bulletproof IP they need to deliver against impossible odds. Ask our competitors. Nobody does what we do.
PHY Integration: No Shortcuts, Stronger Results
No Shortcuts, Stronger Results PHY Integration is an essential process for any design and technology project. Setting it up right the first time is both the fastest and most efficient way you can be confident in your product long-term. We’ll tell you how we do it, how we ensure that it works, and how we’re the best people to get it done. Step-by-Step Expertise Common-sense principles of chip design tell us that the most recently developed portion of ...
Trilinear Technologies Gen6 Release
New DisplayPort Controllers Include DisplayPort 2.0, Embedded DisplayPort 1.5, and Integrated DSC 1.2a Support
We’re adding display stream compression (DSC) encode and decode solutions to our IP portfolio.
Meet the newest members of its M-series video compression IP core family, the M25 DSC 1.2 Decoder and M27 DSC 1.2 Encoder. With its high performance, low cost implementation, the Display Stream Compression encoder and decoder cores can be integrated into System-on-Chips (SoCs) or FPGAs for a wide range of applications including consumer electronics, professional video editing, broadcast, medical and surveillance applications. The Trilinear Technologies DSC encoder and decoder cores provide a balance of processing clock rate and resource usage ...
We’re advancing industry-leading DisplayPort transmitter and receiver link controllers.
Continuing the highly successful line of DisplayPort link controller cores, the Trilinear VF-111T DisplayPort Transmitter and VF-117R DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.4 standard. The fifth generation cores are available for implementation in FPGA or ASIC devices utilizing a variety of physical layer (PHY) interfaces available through third party partners. Both the Transmitter and Receiver are currently implemented for evaluation in multiple FPGA platforms. The fifth generation ...
We’re delivering next-generation DisplayPort controllers for multiple FPGA and ASIC tech.
Big stuff! Our VF-111T DisplayPort Transmitter and VF-117R DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.3a standard and the Embedded DisplayPort 1.4 standard. With the latest round of improvements, Trilinear has added compliance with the latest VESA standards and support for multiple silicon PHY implementations available in process nodes from 55nm to 14nm. Both cores are currently implemented for evaluation in Xilinx FPGAs. The new generation of Trilinear DisplayPort ...
