Meet the newest members of its M-series video compression IP core family, the M25 DSC 1.2 Decoder and M27 DSC 1.2 Encoder. With its high performance, low cost implementation, the Display Stream Compression encoder and decoder cores can be integrated into System-on-Chips (SoCs) or FPGAs for a wide range of applications including consumer electronics, professional video editing, broadcast, medical and surveillance applications.
The Trilinear Technologies DSC encoder and decoder cores provide a balance of processing clock rate and resource usage for efficient ASIC and FPGA implementations. The M25 and M27 cores are fully compliant with the Video Electronics Standards Association (VESA) Display Stream Compression 1.2 standard. Both cores include a proprietary multi-pass processing algorithm which provides high performance processing at a significantly reduced gate count. The cores also provide fully autonomous operation with low software maintenance requirements.
“Trilinear has been delivering high-performance and cost-effective digital video solutions into the marketplace for the past 10 years,” said Carl Ruggiero, chief executive officer at Trilinear Technologies, Inc. “The M25 and M27 IP cores integrate all of our combined experience into a powerful and low resource solution unrivalled in the industry. These new products will help to bring DSC technology to low cost ASIC applications as well as FPGA applications allowing our customers to improve their video products.”
The Trilinear M25 and M27 DSC cores are demonstrated with the Cobra Development System which includes a complete Software Development Kit (SDK) featuring real time application software for the evaluation of core performance. The development system includes a host processor and peripheral suite controlled via the TRIMON ROM monitor. TRIMON is a full-featured monitor with a robust API that offers driver level access to the onboard hardware. The SDK includes a complete reference driver and sample application code in a real-time processing environment.