Categories: Product Launch

Delivering Next-Generation DisplayPort Controllers for Multiple FPGA and ASIC Tech

Nov 3rd, 2020 – Our latest DisplayPort Transmitter and DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.3a standard and the Embedded DisplayPort 1.4 standard. With the latest round of improvements, Trilinear has added compliance with the latest VESA standards and support for multiple silicon PHY implementations available in process nodes from 55nm to 14nm. Both cores are currently implemented for evaluation in Xilinx FPGAs.

The new generation of Trilinear DisplayPort link controllers provides a highly advanced set of functionality including complete support for DisplayPort 1.3a featuring the HBR3 data rate, Multiple Stream Transport (MST) and HDCP 2.2 encryption and decryption engines. Improved support for Embedded DisplayPort 1.4 has also been included with Panel Self-Refresh modes 1 and 2, Advanced Link Power Management, Multi-Touch over AUX as well as full support for all secondary channel packet types. As with the previous generation of DisplayPort solutions, the new link controllers are highly configurable and include full standards compliance. Both cores are available for licensing now. The IP is silicon proven licensed by multiple lead customers.

As with all previous generations of the Trilinear DisplayPort link controllers, the latest cores provide a unique internal architecture that allows integration into both FPGA and ASIC target environments with no loss of performance. This allows for reliable ASIC prototyping as well as the deployment of production quality solutions in FPGA. Low CPU overhead for each core and standard interfaces such as the AMBA APB-3 allow for easy integration into existing or new designs.

In addition to the advanced functionality of the new DisplayPort Intellectual Property cores, Trilinear Technologies has included support for a wide range of silicon PHY solutions from multiple partners. “Selecting the proper PHY for integration with a DisplayPort link controller is a major consideration in any DisplayPort design”, said Carl Ruggiero, CEO for Trilinear Technologies. “Our engineers have made great strides in providing support for a wide range of solutions from 55 nanometer down to 14 nanometer process targets. The fact that we support multiple third party PHY implementation as well as customer developed implementations make these cores some of the most versatile in the market.”

The Trilinear DisplayPort cores are available for demonstration on the FPGA-based Cobra Development System with a complete Software Development Kit (SDK) featuring the DisplayPort-compliant Link Manager. The Cobra development system supports full transmitter and receiver core validation environments and allows for real time testing of all supported lane count and link rate configurations.


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