Connectivity Products

DSC Encoder

The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel input using either RGB or YCbCr in 4:4:4 or 4:2:2 format. The DSC Encoder core integrates industry standard interfaces for host configuration and control, video input, and output.

Cores against chaos.

  • Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
  • Low gate count and low latency implementation
  • Three clock domains
    • Stream and APB clocks operate the applicable interfaces
    • Independent decoder clock runs the core functions
  • Fully compliant with the VESA DSC 1.2 standard
  • Uses synchronous design techniques and a technology abstraction layer for internal SRAM buffers
  • Allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core
  • Completely pipelined; can be stalled as necessary to properly manage input and output rates
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