Trilinear partners with SRES, industry leaders in functional safety standards, to offer DisplayPort IP that is proven ISO 26262 ASIL B ready

PHY Integration is an essential process for any design and technology project. Setting it up right the first time is both the fastest and most efficient way you can be confident in your product long-term. We’ll tell you how we do it, how we ensure that it works, and how we’re the best people to get it done.  

Continuing the highly successful line of DisplayPort link controller cores, the Trilinear VF-111T DisplayPort Transmitter and VF-117R DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.4 standard. The fifth generation cores are available for implementation in FPGA or ASIC devices utilizing a variety of physical layer (PHY) interfaces available through third party partners. Both the Transmitter and Receiver are currently implemented for evaluation in multiple FPGA platforms.