Connectivity Products

DisplayPort Transmitter

Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4-2.1 and embedded DisplayPort 1.5 features, including link rates up to 20Gbps, Display Stream Compression (DSC 1.2), multi-stream transport (MST) and more. The base core includes all required link functionality—Main Link, Secondary Channel, and AUX Channel protocols—and supports the HDCP 1.3 and HDCP 2.2/2.3 standards for data encryption.

The DisplayPort Transmitter core interfaces use common industry standards for low-complexity integration.

Cores against chaos.

  • Silicon proven on multiple ASIC and FPGA processes with multiple PHY partners.
  • Link Controller core supports DisplayPort 2.1,
    DisplayPort 1.4a and embedded DisplayPort 1.5
  • 1, 2 or 4 pixels per input cycle, supporting up to 16K resolution input per source
  • 1.62-20Gbps (8.1Gbps max for 1.4a)
    link rate across 1, 2, or 4 lanes
  • SST or MST operation
  • Full secondary channel support
  • Real time HDCP 1.3/2.2/2.3 support
  • Deep color and HDR support
  • DSC transport with Forward Error Correction support
  • Interfaces to external PHY. Compatible with 3rd-party PHYs for ASICs from 7nm to 65nm technologies. FPGA targeted implementations are also available.

Full Product Brief