Cores Support Real-Time DSC 1.2 Compliant Operations
LAKE OSWEGO, Ore. – January 5, 2017 – Imaging and display intellectual property (IP) provider, Trilinear TechnologiesTM, Inc., today announced the newest members of its M-series video compression IP core family, the M25 DSC 1.2 Decoder and M27 DSC 1.2 Encoder. With its high performance, low cost implementation, the Display Stream Compression encoder and decoder cores can be integrated into System-on-Chips (SoCs) or FPGAs for a wide range of applications including consumer electronics, professional video editing, broadcast, medical and surveillance applications.
The Trilinear Technologies DSC encoder and decoder cores provide a balance of processing clock rate and resource usage for efficient ASIC and FPGA implementations. The M25 and M27 cores are fully compliant with the Video Electronics Standards Association (VESA) Display Stream Compression 1.2 standard. Both cores include a proprietary multi-pass processing algorithm which provides high performance processing at a significantly reduced gate count. The cores also provide fully autonomous operation with low software maintenance requirements.
“Trilinear has been delivering high-performance and cost-effective digital video solutions into the marketplace for the past 10 years,” said Carl Ruggiero, chief executive officer at Trilinear Technologies, Inc. “The M25 and M27 IP cores integrate all of our combined experience into a powerful and low resource solution unrivalled in the industry. These new products will help to bring DSC technology to low cost ASIC applications as well as FPGA applications allowing our customers to improve their video products.”
The Trilinear M25 and M27 DSC cores are demonstrated with the Cobra Development System which includes a complete Software Development Kit (SDK) featuring real time application software for the evaluation of core performance. The development system includes a host processor and peripheral suite controlled via the TRIMON ROM monitor. TRIMON is a full-featured monitor with a robust API that offers driver level access to the onboard hardware. The SDK includes a complete reference driver and sample application code in a real-time processing environment.
Availability and Pricing
The Trilinear M25 DSC 1.2 Decoder and M27 DSC 1.2 Encoder are currently in production. The cores are available as a standalone product or as an additional feature of the widely-adopted Trilinear Technologies DisplayPort 1.4 Transmitter and Receiver cores. The cores are shipped with a complete reference driver as well as application layer sample code. For more information about the product, its pricing and how to purchase, please visit http://www.trilineartech.com.
About the Display Stream Compression Standard
VESA, the Video Electronics Standards Association, has published a new Standard in 2014 that uses visually lossless image compression to increase the amount of data carried by a display interface data rate, saving power. DSC achieves visually lossless compression quality at a low compression ratio by using a much simpler codec (coder/decoder) circuit. The typical compression ratio of DSC range from 1:1 to about 3:1 which offers significant benefit in interface data rate reduction. The current version of the standard is DSC 1.2 and was approved January 20, 2016.
About Trilinear Technolgies, Inc.
Trilinear Technologies Inc., headquartered in Portland, Ore. and privately funded, is a premier provider of soft IP cores for ASIC implementation and FPGA prototyping. The company services the broadcast, consumer display, medical, mobile devices, military, and security markets. Trilinear’s IP cores enable customers producing high quality chips to enjoy faster product design, shorter time-to-market, and overall cost reduction. The company sells its products through a network of distributors. For more information about the company and its products, please visit http://www.trilineartech.com.
Trilinear is a trademark of Trilinear Technologies, Inc. All other trademarks are the property of their respective owners.